The fabrication of silicon-on-insulator ("SOI") substrates or wafers using separation by implantation of oxygen ("SIMOX") involves the implantation of oxygen ions into a silicon bulk substrate to create a buried insulator layer or buried oxide layer ("BOX") below the upper surface of the silicon bulk substrate. As a result, an active SOI region is formed in the single-crystalline silicon bulk substrate located above the BOX. This area may be referred to as an SOI layer or film. The SIMOX process generally involves three steps: (1) cleaning a standard silicon wafer; (2) implanting oxygen ions under the surface of the wafer or substrate using a relatively high energy ion beam at around 200 keV at a dose of O.sup.+ of around 2.times.10.sup.18 /cm.sup.2 ; and (3) annealing the wafer at a high temperature that is greater than around 1300.degree. C. for around six hours to help remove damage caused by the oxygen ion implantation.
SIMOX is generally the preferred process for building SOI substrates or wafers. SOI substrates can be used, for example, in very large scale integration ("VLSI") devices and ultra large scale integration ("ULSI") devices. SOI substrates or wafers generally provide, for example, one or more of the following advantages over bulk silicon wafers: (1) better radiation hardness; (2) higher speed performance; (3) higher temperature operations; (4) lower power devices; (5) lower cost process for some applications; and (6) easier implementation of submicrometer design rules. Furthermore, patterned SOI substrates or wafers provide additional advantages that include the ability to fabricate devices made from different technologies on a single substrate. This may include the implementation of smart power devices, mixed signal devices, and other devices that would require a high voltage isolation. Patterned SOI substrates refer to substrates that include active SOI regions, for building devices in an active SOI region, and active bulk substrate regions, for building devices in an active bulk substrate region.
The fabrication of patterned SOI substrates or wafers using SIMOX involves the selective implantation of oxygen ions into a silicon bulk substrate to produce active SOI regions and active bulk substrate regions. The active SOI regions are formed above a buried oxide layer ("BOX") that is formed as a result of the implantation of oxygen ions. Active SOI regions include an SOI film or layer of single-crystalline silicon that is present between the upper surface of the BOX and the upper surface of the silicon bulk substrate. However, the implantation of oxygen ions damages the silicon bulk substrate. Of particular interest are damaged areas created in the bulk substrate that are located in transition regions between active SOI regions and active bulk substrate regions. As a consequence, devices may not be fabricated in the damaged areas resulting in a significant amount of unavailable or non-productive wafer area. This significantly reduces overall integrated circuitry density.
The BOX, present in each active SOI region, has an upper and a lower surface and sides. The formation of the BOX below the surface of the silicon bulk substrate generates internal stresses due to the uneven expansion of the BOX during the SIMOX process. These internal stresses result in crystalline dislocations extending outwardly from all sides of the BOX which result in the formation of the damaged areas. Normally, the SOI wafer is annealed after oxygen implantation to allow some of the crystalline dislocations to be removed. However, the crystalline dislocations extending outwardly from the sides of the BOX and extending into both the active SOI region and the adjacent active bulk substrate region will not be removed by annealing. As a result of the implantation of oxygen ions, the transition region between an active SOI region and an active bulk substrate region is characterized by a large number of crystalline dislocations which define the damaged area. The damaged area extends into both the active SOI region and the active bulk substrate region and is not suitable for fabricating devices. These crystalline dislocations cause undesirable leakage currents. Hence, the overall circuitry design must provide for sufficient device spacing to avoid these damaged areas. This significantly reduces overall wafer or die area available for device fabrication.